The asureISG tool from T&VS accelerates the completion of CPU code-coverage and helps discover bugs that often go unnoticed with traditional directed testing.
The tool includes support for:
- Event generation for mimicking complex system (e.g. sensor inputs)
- Random generation of structures (e.g., directed graphs)
- Developed in pure C++
- Directly generate:
- Directed instruction assembly
- Constrained Random instruction assembly
- Special scenarios to verify CPU performance and corner cases
- Generate cases with sequences, constraints and policies
- Generate performance monitoring instruction streams, including:
- Various kinds of inputs, resources, resource sharing, etc.
- Configure specialized streams for specific unit-level instruction verification